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mini2440之ADS下DMA測試

日期:2017/3/1 11:15:42   编辑:Linux編程

找到一個dma的ads工程,將其dma功能整到了原來的ads工程TQ2440_Test裡面
用Linux公社(Linuxidc.com)提供的main.c替換原來TQ2440_Test的main.c

main.c下載地址:

下載在Linux公社的1號FTP服務器裡,下載地址:

FTP地址:ftp://www.linuxidc.com

用戶名:www.linuxidc.com

密碼:www.muu.cc

在 2011年LinuxIDC.com\10月\mini2440之ADS下DMA測試

下載方法見 http://www.linuxidc.net/thread-1187-1-1.html

之所以要介紹DMA,因為它對性能太重要了!只有活用了DMA,CPU的性能才能上去!S3c2410有四個DMA,每個DMA支持工作方式基本相同,但支持的source Dest可能略有不同,具體見Datasheet。

這裡具體DMA CONTROL寄存器(DCON)的配置說明,進而引出DMA的各種工作方式。

Atomic transfer:指的是DMA的單次原子操作,它可以是Unit模式(傳輸1個data size),也可以是burst模式(傳輸4個data size),具體對應DCON[28]。

Data Size:指的是單次原子操作的數據位寬,8、16、32,具體對應DCON[21:20]。

Request Source:DMA請求的來源有兩種,軟件&硬件模塊,由DCON[23]控制;當為前者時,由軟件對DMASKTRIG寄存器的位0置位觸發一次DMA 操作。當為後者時,具體來源由DCON[26:24]控制,不同硬件模塊的某時間觸發一次DMA操作,具體要見不同的硬件模塊。

DMA service mode:DMA的工作模式有兩種,單一服務模式&整體服務模式。前一模式下,一次DMA請求完成一項原子操作,並且transfer count的值減1。後一模式下,一次DMA請求完成一批原子操作,直到transfer count等於0表示完成一次整體服務。具體對應DCON[27]。

RELOAD:在reload模式下,當transfer count的值變為零時,將自動加src、dst、TC的值加載到CURR_DST、CURR_SRC、CURR_TC,並開始一次新的DMA傳輸。該模式一般和整體服務模式一起使用,也就是說當一次整體服務開始後,src、dst、TC的值都已經被加載,因此可以更改為下一次

服務的地址,2410說明文檔中建議加入以下語句來判斷當前的服務開始,src、dst、TC的值可以被更改了:while((rDSTATn & 0xfffff) == 0) ;

Req&Ack:DMA請求和應答的協議有兩種,Demard mode 和 Handshake mode。兩者對Request和Ack的時序定義有所不同:在Demard模式下,如果

DMA完成一次請求如果Request仍然有效,那麼DMA就認為這是下一次DMA請求;在Handshake模式下,DMA完成一次請求後等待Request信號無效,然後把ACK也置無效,再等待下一次Request。這個設計外部DMA請求時可能要用到。

傳輸總長度:DMA一次整體服務傳輸的總長度為:

Data Size × Atomic transfer size × TC(字節)。

  1. /****************************************************************
  2. NAME: u2440mon.c
  3. DESC: u2440mon entry point,menu,download
  4. ****************************************************************/
  5. #define GLOBAL_CLK 1
  6. #include <stdlib.h>
  7. #include <string.h>
  8. #include "def.h"
  9. #include "option.h"
  10. #include "2440addr.h"
  11. #include "2440lib.h"
  12. #include "2440slib.h"
  13. #include "mmu.h"
  14. #include "profile.h"
  15. #include "memtest.h"
  16. extern char Image$RO$Limit[];
  17. extern char Image$RO$Base[];
  18. extern char Image$RW$Limit[];
  19. extern char Image$RW$Base[];
  20. extern char Image$ZI$Limit[];
  21. extern char Image$ZI$Base[];
  22. void Isr_Init(void);
  23. void HaltUndef(void);
  24. void HaltSwi(void);
  25. void HaltPabort(void);
  26. void HaltDabort(void);
  27. void ClearMemory(void);
  28. void Clk0_Enable(int clock_sel);
  29. void Clk1_Enable(int clock_sel);
  30. void Clk0_Disable(void);
  31. void Clk1_Disable(void);
  32. extern void Lcd_TFT_Init(void);
  33. extern void Lcd_TFT_Test( void ) ;
  34. extern void Test_Touchpanel(void) ;
  35. extern void Test_Adc(void) ;
  36. extern void KeyScan_Test(void) ;
  37. extern void RTC_Display(void) ;
  38. extern void Test_IrDA_Tx(void) ;
  39. extern void PlayMusicTest(void) ;
  40. extern void RecordTest( void ) ;
  41. extern void Test_Iic(void) ;
  42. extern void Test_SDI(void) ;
  43. extern void Camera_Test( void ) ;
  44. volatile U32 downloadAddress;
  45. void (*restart)(void)=(void (*)(void))0x0;
  46. volatile unsigned char *downPt;
  47. volatile U32 downloadFileSize;
  48. volatile U16 checkSum;
  49. volatile unsigned int err=0;
  50. volatile U32 totalDmaCount;
  51. volatile int isUsbdSetConfiguration;
  52. int download_run=0;
  53. U32 tempDownloadAddress;
  54. int menuUsed=0;
  55. extern char Image$RW$Limit[];
  56. U32 *pMagicNum=(U32 *)Image$RW$Limit;
  57. int consoleNum;
  58. static U32 cpu_freq;
  59. static U32 UPLL;
  60. static void cal_cpu_bus_clk(void)
  61. {
  62. U32 val;
  63. U8 m, p, s;
  64. val = rMPLLCON;
  65. m = (val>>12)&0xff;
  66. p = (val>>4)&0x3f;
  67. s = val&3;
  68. //(m+8)*FIN*2 不要超出32位數!
  69. FCLK = ((m+8)*(FIN/100)*2)/((p+2)*(1<<s))*100;
  70. val = rCLKDIVN;
  71. m = (val>>1)&3;
  72. p = val&1;
  73. val = rCAMDIVN;
  74. s = val>>8;
  75. switch (m) {
  76. case 0:
  77. HCLK = FCLK;
  78. break;
  79. case 1:
  80. HCLK = FCLK>>1;
  81. break;
  82. case 2:
  83. if(s&2)
  84. HCLK = FCLK>>3;
  85. else
  86. HCLK = FCLK>>2;
  87. break;
  88. case 3:
  89. if(s&1)
  90. HCLK = FCLK/6;
  91. else
  92. HCLK = FCLK/3;
  93. break;
  94. }
  95. if(p)
  96. PCLK = HCLK>>1;
  97. else
  98. PCLK = HCLK;
  99. if(s&0x10)
  100. cpu_freq = HCLK;
  101. else
  102. cpu_freq = FCLK;
  103. val = rUPLLCON;
  104. m = (val>>12)&0xff;
  105. p = (val>>4)&0x3f;
  106. s = val&3;
  107. UPLL = ((m+8)*FIN)/((p+2)*(1<<s));
  108. UCLK = (rCLKDIVN&8)?(UPLL>>1):UPLL;
  109. }
  110. /****************************************************************************************************************/
  111. static volatile unsigned done;
  112. struct reg
  113. {
  114. volatile U32 DISRC;//初始原基地址寄存器
  115. volatile U32 DISRCC;//初始源控制寄存器
  116. volatile U32 DIDST;//初始目的基地址寄存器
  117. volatile U32 DIDSTC;//初始目的控制寄存器
  118. volatile U32 DCON;//dma控制寄存器
  119. volatile U32 DSTAT;//狀態/計數寄存器
  120. volatile U32 DCSRC;//當前源地址寄存器
  121. volatile U32 DCDST;//當前目的地址寄存器
  122. volatile U32 DMASKTRIG;//dma掩碼,觸發寄存器
  123. };//用於描述某個dma通道的9個寄存器
  124. /*
  125. 此timer用於計時,使用了看門狗定時器
  126. watchdog timer看門狗也是一個定時器,比普通定時器多了一個功能,就是在定時器定時結束時會觸發
  127. 一個特殊的事件:重啟cpu
  128. */
  129. void timer_start(int time)
  130. {
  131. rWTCON=((PCLK/1000000-1)<<8)|(time<<3);
  132. //rWTCON=((PCLK-1)<<8)|(time<<3);
  133. rWTCNT=0xffff;
  134. rWTDAT=0xffff;
  135. rWTCON=rWTCON &~(1<<5)&~(1<<2)|(1<<5);
  136. }
  137. /*
  138. rWTCON
  139. b8-b15,預分頻值
  140. b3-b4,
  141. 時鐘分頻選擇
  142. 00,16
  143. 01,32
  144. 10,64
  145. 11,128*
  146. b5=1,enable watch dog timer
  147. b2=0,disable watch dog timer interrupt
  148. 一般
  149. fclk=400MHZ
  150. hclk=100MHZ
  151. pclk=50MHZ
  152. 可用輸出看一下本板子的頻率
  153. Uart_Printf("FCLK=%d,HCLK=%d,PCLK=%d\n",FCLK,HCLK,PCLK );
  154. FCLK=400000000,HCLK=100000000,PCLK=50000000
  155. 相關寄存器的設置在其他地方
  156. cal_cpu_bus_clk來查詢相關寄存器以確定fclk,hclk,pclk
  157. rWTCON高8位設置為50x10^6/10^6-1=49,//用PCLK/1000000-1設置其高8位,即使PCLK變化,狗的時間計算方法也不必變
  158. 時鐘分頻選擇11為128
  159. 根據2440 spec 狗的周期為 t_watchdog = 1/[ PCLK / (Prescaler value + 1) / Division_factor ]=128*10^(-6) S=128/1000ms
  160. 所以有如下計算所用時間的公式
  161. src_to_dst=timer_stop()
  162. Uart_Printf("DMA transfer done time=%u MS\n",src_to_dst*128/1000);
  163. */
  164. int timer_stop(void)
  165. {
  166. rWTCON=((PCLK/1000000-1)<<8);
  167. return (0xffff-rWTCNT);
  168. }
  169. /*
  170. 本例使用dma傳輸數據的步驟
  171. 1.指定dma傳輸完成中斷處理函數,設置源目的寄存器,傳輸次數,傳輸模式等
  172. 2.向cpu發出dma傳輸請求信號,請求cpu將總線控制權交釋放,dma控制器控制數據在兩個內存區間經由總線傳輸,
  173. 可以是外部引腳請求dma傳輸,
  174. 也可以是設置寄存器DMASKTRIG b0來產生請求dma傳輸
  175. 到底是哪個,由寄存器DCON b23決定
  176. 3.比如dma0傳輸完成,則自動產生dma0中斷請求信號,要在中斷處理程序中手動清除中斷請求位
  177. */
  178. void __irq DMA0done(void)
  179. {
  180. done=1;
  181. ClearPending(BIT_DMA0);
  182. }
  183. void __irq DMA1done(void)
  184. {
  185. done=1;
  186. ClearPending(BIT_DMA1);
  187. }
  188. void __irq DMA2done(void)
  189. {
  190. done=1;
  191. ClearPending(BIT_DMA2);
  192. }
  193. void __irq DMA3done(void)
  194. {
  195. done=1;
  196. ClearPending(BIT_DMA3);
  197. }
  198. void DMA_move(int ch,int srcaddr,int dstaddr,int tc,int dsz,int tsz)
  199. {
  200. int i;
  201. struct reg *pDMA;
  202. int src_to_dst;
  203. int sum0=0,sum1=0;
  204. int length;
  205. length=tc*((tsz)?4:1)*((dsz==0)*1+(dsz==1)*2+(dsz==2)*4);
  206. /*tc傳輸次數
  207. tsz每次傳輸幾個數據類型,tsz=0為1個,tsz=1為4個
  208. dsz傳輸的數據類型,dsz=0為字節,dsz=1為半字,dsz=2為字,dsz=3未指定
  209. 所以有上面的length計算
  210. 見2440 spec
  211. */
  212. switch(ch)
  213. {
  214. case 0:
  215. pISR_DMA0=(unsigned)DMA0done;//指定dma0中斷處理程序為DMA0done
  216. EnableIrq(BIT_DMA0);//允許dma0通道產生數據傳輸完成中斷(設置中斷掩碼寄存器0x4a000008)
  217. pDMA=(void *)0x4b000000;//使pDMA指向通道0的9個寄存器
  218. break;
  219. case 1:
  220. pISR_DMA1=(unsigned)DMA1done;
  221. EnableIrq(BIT_DMA1);
  222. pDMA=(void *)0x4b000040;
  223. break;
  224. case 2:
  225. pISR_DMA2=(unsigned)DMA2done;
  226. EnableIrq(BIT_DMA2);
  227. pDMA=(void *)0x4b000080;
  228. break;
  229. case 3:
  230. pISR_DMA3=(unsigned)DMA3done;
  231. EnableIrq(BIT_DMA3);
  232. pDMA=(void *)0x4b0000c0;
  233. break;
  234. default:
  235. Uart_Printf("channel error\n");
  236. break;
  237. }
  238. for(i=srcaddr;i<(srcaddr+length);i+=4)//sum0和sum1用於校驗傳輸是夠正確
  239. {
  240. *((U32 *)i)=i^0x55aa5aa5;//按位異或
  241. sum0+=i^0x55aa5aa5;
  242. }
  243. Uart_Printf("DMA%d %8xh->%8xh,size=%xh(tc=%xh),dsz=%d,burst=%d\n",ch,
  244. srcaddr,dstaddr,length,tc,dsz,tsz);
  245. done=0;
  246. pDMA->DISRC=srcaddr;//源地址
  247. pDMA->DISRCC=(0<<1)|(0<<0);//源地址所在總線為ahb,源地址自動增加 0 或1 2 4(由dsz定)
  248. pDMA->DIDST=dstaddr;//目的地址
  249. pDMA->DIDSTC=(0<<1)|(0<<0);//目的地址所在總線為ahb,目的地址自動增加0 或1 2 4(由dsz定)
  250. pDMA->DCON=(1<<31)|(1<<30)|(1<<29)|(tsz<<28)|(1<<27)|(0<<23)|(1<<22)|(dsz<<20)|(tc);
  251. /*
  252. b31=1單服務握手
  253. b30=1與hclk同步,高速外設
  254. b29=1當所有的傳輸結束時,產生中斷請求
  255. b28=tsz ,每次所要傳輸的數據類型個數
  256. tsz=1,執行4數據長的突發傳輸 boost
  257. tsz=0.執行單數據傳輸
  258. note:dma執行期間,和cpu可以交替占有總線
  259. b27=1,全服務傳輸,不查詢dreq,但傳輸一次也要釋放總線
  260. b23=0,由軟件方式產生dma請求,需要用DMASKTRIG寄存器的SW_TRIG位置1觸發
  261. b21-b20=dsz,每次傳輸的數據類型設置
  262. dsz=00,字節
  263. dsz=01,半字
  264. dsz=10,字
  265. dsz=11,保留
  266. b19-b0=tc,傳輸次數,每次自動減1,直至減到0,便產生dma傳輸完成中斷**********************
  267. */
  268. pDMA->DMASKTRIG=(1<<1)|(1);
  269. /*
  270. b1=1,開放通道
  271. b0=1,此b0是dma軟件觸發位,實現軟件觸發dma請求
  272. */
  273. timer_start(3);//開始計時
  274. while(done==0);//在done=1之前cpu一直在此循環,實際中的dma傳輸計時不可能是這樣,dma傳輸期間,cpu可以可以去執行其他任務
  275. src_to_dst=timer_stop();//停止計時,返回本次dma傳輸所用時間
  276. Uart_Printf("DMA transfer done time=%u MS\n",src_to_dst*128/1000);
  277. DisableIrq(BIT_DMA0);
  278. DisableIrq(BIT_DMA1);
  279. DisableIrq(BIT_DMA2);
  280. DisableIrq(BIT_DMA3);
  281. for(i=dstaddr;i<(dstaddr+length);i+=4)
  282. sum1+=i^0x55aa5aa5;
  283. Uart_Printf("sum0=%2x,sum1=%2x\n",sum0,sum1);
  284. if(sum0==sum1)
  285. Uart_Printf("DMA test OK\n");
  286. else
  287. Uart_Printf("DMA test failured\n");
  288. }
  289. void DMA_test(void)
  290. {
  291. DMA_move(0,_NONCACHE_STARTADDRESS,_NONCACHE_STARTADDRESS+0x800000,0x80000,0,0); //byte,single
  292. DMA_move(0,_NONCACHE_STARTADDRESS,_NONCACHE_STARTADDRESS+0x800000,0x40000,1,0); //halfword,single
  293. DMA_move(0,_NONCACHE_STARTADDRESS,_NONCACHE_STARTADDRESS+0x800000,0x20000,2,0); //word,single
  294. DMA_move(0,_NONCACHE_STARTADDRESS,_NONCACHE_STARTADDRESS+0x800000,0x20000,0,1); //byte,burst
  295. DMA_move(0,_NONCACHE_STARTADDRESS,_NONCACHE_STARTADDRESS+0x800000,0x10000,1,1); //halfword,burst
  296. DMA_move(0,_NONCACHE_STARTADDRESS,_NONCACHE_STARTADDRESS+0x800000, 0x8000,2,1); //word,burst
  297. //DMA Ch 1
  298. DMA_move(1,_NONCACHE_STARTADDRESS,_NONCACHE_STARTADDRESS+0x800000,0x80000,0,0); //byte,single
  299. DMA_move(1,_NONCACHE_STARTADDRESS,_NONCACHE_STARTADDRESS+0x800000,0x40000,1,0); //halfword,single
  300. DMA_move(1,_NONCACHE_STARTADDRESS,_NONCACHE_STARTADDRESS+0x800000,0x20000,2,0); //word,single
  301. DMA_move(1,_NONCACHE_STARTADDRESS,_NONCACHE_STARTADDRESS+0x800000,0x20000,0,1); //byte,burst
  302. DMA_move(1,_NONCACHE_STARTADDRESS,_NONCACHE_STARTADDRESS+0x800000,0x10000,1,1); //halfword,burst
  303. DMA_move(1,_NONCACHE_STARTADDRESS,_NONCACHE_STARTADDRESS+0x800000, 0x8000,2,1); //word,burst
  304. //DMA Ch 2
  305. DMA_move(2,_NONCACHE_STARTADDRESS,_NONCACHE_STARTADDRESS+0x800000,0x80000,0,0); //byte,single
  306. DMA_move(2,_NONCACHE_STARTADDRESS,_NONCACHE_STARTADDRESS+0x800000,0x40000,1,0); //halfword,single
  307. DMA_move(2,_NONCACHE_STARTADDRESS,_NONCACHE_STARTADDRESS+0x800000,0x20000,2,0); //word,single
  308. DMA_move(2,_NONCACHE_STARTADDRESS,_NONCACHE_STARTADDRESS+0x800000,0x20000,0,1); //byte,burst
  309. DMA_move(2,_NONCACHE_STARTADDRESS,_NONCACHE_STARTADDRESS+0x800000,0x10000,1,1); //halfword,burst
  310. DMA_move(2,_NONCACHE_STARTADDRESS,_NONCACHE_STARTADDRESS+0x800000, 0x8000,2,1); //word,burst
  311. //DMA Ch 3
  312. DMA_move(3,_NONCACHE_STARTADDRESS,_NONCACHE_STARTADDRESS+0x800000,0x80000,0,0); //byte,single
  313. DMA_move(3,_NONCACHE_STARTADDRESS,_NONCACHE_STARTADDRESS+0x800000,0x40000,1,0); //halfword,single
  314. DMA_move(3,_NONCACHE_STARTADDRESS,_NONCACHE_STARTADDRESS+0x800000,0x20000,2,0); //word,single
  315. DMA_move(3,_NONCACHE_STARTADDRESS,_NONCACHE_STARTADDRESS+0x800000,0x20000,0,1); //byte,burst
  316. DMA_move(3,_NONCACHE_STARTADDRESS,_NONCACHE_STARTADDRESS+0x800000,0x10000,1,1); //halfword,burst
  317. DMA_move(3,_NONCACHE_STARTADDRESS,_NONCACHE_STARTADDRESS+0x800000, 0x8000,2,1);
  318. }
  319. /****************************************************************************************************************/
  320. void Temp_function()
  321. { Uart_Printf("\nPlease input 1-11 to select test!!!\n"); }
  322. struct {
  323. void (*fun)(void);
  324. char *tip;
  325. }CmdTip[] = {
  326. { Temp_function, "Please input 1-11 to select test,song" } ,
  327. { BUZZER_PWM_Test, "Test PWM" } ,
  328. { RTC_Display, "RTC time display" } ,
  329. { Test_Adc, "Test ADC" } ,
  330. { KeyScan_Test, "Test interrupt and key scan" } ,
  331. { Test_Touchpanel, "Test Touchpanel" } ,
  332. { Lcd_TFT_Test, "Test TFT LCD" } ,
  333. { Test_Iic, "Test IIC EEPROM" } ,
  334. { PlayMusicTest, "UDA1341 play music" } ,
  335. { RecordTest, "UDA1341 record voice" } ,
  336. { Test_SDI, "Test SD Card" } ,
  337. { Camera_Test, "Test CMOS Camera"},
  338. { DMA_test, "Test dma"};//add by song
  339. { 0, 0}
  340. };
  341. void Main(void)
  342. {
  343. char *mode;
  344. int i;
  345. U8 key;
  346. U32 mpll_val = 0 ;
  347. //U32 divn_upll = 0 ;
  348. #if ADS10
  349. // __rt_lib_init(); //for ADS 1.0
  350. #endif
  351. Port_Init();
  352. Isr_Init();
  353. i = 2 ; //don't use 100M!
  354. switch ( i ) {
  355. case 0: //200
  356. key = 12;
  357. mpll_val = (92<<12)|(4<<4)|(1);
  358. break;
  359. case 1: //300
  360. key = 13;
  361. mpll_val = (67<<12)|(1<<4)|(1);
  362. break;
  363. case 2: //400
  364. key = 14;
  365. mpll_val = (92<<12)|(1<<4)|(1);
  366. break;
  367. case 3: //440!!!
  368. key = 14;
  369. mpll_val = (102<<12)|(1<<4)|(1);
  370. break;
  371. default:
  372. key = 14;
  373. mpll_val = (92<<12)|(1<<4)|(1);
  374. break;
  375. }
  376. //init FCLK=400M, so change MPLL first
  377. ChangeMPllValue((mpll_val>>12)&0xff, (mpll_val>>4)&0x3f, mpll_val&3);
  378. ChangeClockDivider(key, 12);
  379. cal_cpu_bus_clk();
  380. consoleNum = 0; // Uart 1 select for debug.
  381. Uart_Init( 0,115200 );
  382. Uart_Select( consoleNum );
  383. Beep(2000, 1000);
  384. Uart_SendByte('\n');
  385. Uart_Printf("<***************************************>\n");
  386. Uart_Printf(" TQ2440 Test Program\n");
  387. Uart_Printf(" www.embedsky.net\n");
  388. Uart_Printf(" Build time is: %s %s\n", __DATE__ , __TIME__ );
  389. Uart_Printf("<***************************************>\n");
  390. rMISCCR=rMISCCR&~(1<<3); // USBD is selected instead of USBH1
  391. rMISCCR=rMISCCR&~(1<<13); // USB port 1 is enabled.
  392. rDSC0 = 0x2aa;
  393. rDSC1 = 0x2aaaaaaa;
  394. //Enable NAND, USBD, PWM TImer, UART0,1 and GPIO clock,
  395. //the others must be enabled in OS!!!
  396. rCLKCON = 0xfffff0;
  397. MMU_Init(); //
  398. pISR_SWI=(_ISR_STARTADDRESS+0xf0); //for pSOS
  399. Led_Display(0x66);
  400. mode="DMA";
  401. Clk0_Disable();
  402. Clk1_Disable();
  403. mpll_val = rMPLLCON;
  404. Lcd_TFT_Init() ; // LCD initial
  405. download_run=1; //The default menu is the Download & Run mode.
  406. while(1)
  407. {
  408. U8 idx;
  409. Uart_Printf("\nPlease select function : \n");
  410. for(i=0; CmdTip[i].fun!=0; i++)
  411. Uart_Printf("%d : %s\n", i, CmdTip[i].tip);
  412. idx = Uart_GetIntNum_GJ() ;
  413. if(idx<i)
  414. {
  415. (*CmdTip[idx].fun)();
  416. Delay(20);
  417. Uart_Init( 0,115200 );
  418. }
  419. }
  420. }
  421. void Isr_Init(void)
  422. {
  423. pISR_UNDEF=(unsigned)HaltUndef;
  424. pISR_SWI =(unsigned)HaltSwi;
  425. pISR_PABORT=(unsigned)HaltPabort;
  426. pISR_DABORT=(unsigned)HaltDabort;
  427. rINTMOD=0x0; // All=IRQ mode
  428. rINTMSK=BIT_ALLMSK; // All interrupt is masked.
  429. }
  430. void HaltUndef(void)
  431. {
  432. Uart_Printf("Undefined instruction exception!!!\n");
  433. while(1);
  434. }
  435. void HaltSwi(void)
  436. {
  437. Uart_Printf("SWI exception!!!\n");
  438. while(1);
  439. }
  440. void HaltPabort(void)
  441. {
  442. Uart_Printf("Pabort exception!!!\n");
  443. while(1);
  444. }
  445. void HaltDabort(void)
  446. {
  447. Uart_Printf("Dabort exception!!!\n");
  448. while(1);
  449. }
  450. void ClearMemory(void)
  451. {
  452. int memError=0;
  453. U32 *pt;
  454. Uart_Printf("Clear Memory (%xh-%xh):WR",_RAM_STARTADDRESS,HEAPEND);
  455. pt=(U32 *)_RAM_STARTADDRESS;
  456. while((U32)pt < HEAPEND)
  457. {
  458. *pt=(U32)0x0;
  459. pt++;
  460. }
  461. if(memError==0)Uart_Printf("\b\bO.K.\n");
  462. }
  463. void Clk0_Enable(int clock_sel)
  464. { // 0:MPLLin, 1:UPLL, 2:FCLK, 3:HCLK, 4:PCLK, 5:DCLK0
  465. rMISCCR = rMISCCR&~(7<<4) | (clock_sel<<4);
  466. rGPHCON = rGPHCON&~(3<<18) | (2<<18);
  467. }
  468. void Clk1_Enable(int clock_sel)
  469. { // 0:MPLLout, 1:UPLL, 2:RTC, 3:HCLK, 4:PCLK, 5:DCLK1
  470. rMISCCR = rMISCCR&~(7<<8) | (clock_sel<<8);
  471. rGPHCON = rGPHCON&~(3<<20) | (2<<20);
  472. }
  473. void Clk0_Disable(void)
  474. {
  475. rGPHCON = rGPHCON&~(3<<18); // GPH9 Input
  476. }
  477. void Clk1_Disable(void)
  478. {
  479. rGPHCON = rGPHCON&~(3<<20); // GPH10 Input
  480. }
  1. Please select function :
  2. 0 : Please input 1-11 to select test,song
  3. 1 : Test PWM
  4. 2 : RTC time display
  5. 3 : Test ADC
  6. 4 : Test interrupt and key scan
  7. 5 : Test Touchpanel
  8. 6 : Test TFT LCD
  9. 7 : Test IIC EEPROM
  10. 8 : UDA1341 play music
  11. 9 : UDA1341 record voice
  12. 10 : Test SD Card
  13. 11 : Test CMOS Camera
  14. 12 : Test dma
  15. 12DMA0 31000000h->31800000h,size=80000h(tc=80000h),dsz=0,burst=0
  16. DMA transfer done time=154 MS
  17. sum0=fffe0000,sum1=fffe0000
  18. DMA test OK
  19. DMA0 31000000h->31800000h,size=80000h(tc=40000h),dsz=1,burst=0
  20. DMA transfer done time=77 MS
  21. sum0=fffe0000,sum1=fffe0000
  22. DMA test OK
  23. DMA0 31000000h->31800000h,size=80000h(tc=20000h),dsz=2,burst=0
  24. DMA transfer done time=38 MS
  25. sum0=fffe0000,sum1=fffe0000
  26. DMA test OK
  27. DMA0 31000000h->31800000h,size=80000h(tc=20000h),dsz=0,burst=1
  28. DMA transfer done time=68 MS
  29. sum0=fffe0000,sum1=fffe0000
  30. DMA test OK
  31. DMA0 31000000h->31800000h,size=80000h(tc=10000h),dsz=1,burst=1
  32. DMA transfer done time=34 MS
  33. sum0=fffe0000,sum1=fffe0000
  34. DMA test OK
  35. DMA0 31000000h->31800000h,size=80000h(tc=8000h),dsz=2,burst=1
  36. DMA transfer done time=12 MS
  37. sum0=fffe0000,sum1=fffe0000
  38. DMA test OK
  39. DMA1 31000000h->31800000h,size=80000h(tc=80000h),dsz=0,burst=0
  40. DMA transfer done time=154 MS
  41. sum0=fffe0000,sum1=fffe0000
  42. DMA test OK
  43. DMA1 31000000h->31800000h,size=80000h(tc=40000h),dsz=1,burst=0
  44. DMA transfer done time=77 MS
  45. sum0=fffe0000,sum1=fffe0000
  46. DMA test OK
  47. DMA1 31000000h->31800000h,size=80000h(tc=20000h),dsz=2,burst=0
  48. DMA transfer done time=38 MS
  49. sum0=fffe0000,sum1=fffe0000
  50. DMA test OK
  51. DMA1 31000000h->31800000h,size=80000h(tc=20000h),dsz=0,burst=1
  52. DMA transfer done time=68 MS
  53. sum0=fffe0000,sum1=fffe0000
  54. DMA test OK
  55. DMA1 31000000h->31800000h,size=80000h(tc=10000h),dsz=1,burst=1
  56. DMA transfer done time=34 MS
  57. sum0=fffe0000,sum1=fffe0000
  58. DMA test OK
  59. DMA1 31000000h->31800000h,size=80000h(tc=8000h),dsz=2,burst=1
  60. DMA transfer done time=12 MS
  61. sum0=fffe0000,sum1=fffe0000
  62. DMA test OK
  63. DMA2 31000000h->31800000h,size=80000h(tc=80000h),dsz=0,burst=0
  64. DMA transfer done time=154 MS
  65. sum0=fffe0000,sum1=fffe0000
  66. DMA test OK
  67. DMA2 31000000h->31800000h,size=80000h(tc=40000h),dsz=1,burst=0
  68. DMA transfer done time=77 MS
  69. sum0=fffe0000,sum1=fffe0000
  70. DMA test OK
  71. DMA2 31000000h->31800000h,size=80000h(tc=20000h),dsz=2,burst=0
  72. DMA transfer done time=38 MS
  73. sum0=fffe0000,sum1=fffe0000
  74. DMA test OK
  75. DMA2 31000000h->31800000h,size=80000h(tc=20000h),dsz=0,burst=1
  76. DMA transfer done time=68 MS
  77. sum0=fffe0000,sum1=fffe0000
  78. DMA test OK
  79. DMA2 31000000h->31800000h,size=80000h(tc=10000h),dsz=1,burst=1
  80. DMA transfer done time=34 MS
  81. sum0=fffe0000,sum1=fffe0000
  82. DMA test OK
  83. DMA2 31000000h->31800000h,size=80000h(tc=8000h),dsz=2,burst=1
  84. DMA transfer done time=12 MS
  85. sum0=fffe0000,sum1=fffe0000
  86. DMA test OK
  87. DMA3 31000000h->31800000h,size=80000h(tc=80000h),dsz=0,burst=0
  88. DMA transfer done time=154 MS
  89. sum0=fffe0000,sum1=fffe0000
  90. DMA test OK
  91. DMA3 31000000h->31800000h,size=80000h(tc=40000h),dsz=1,burst=0
  92. DMA transfer done time=77 MS
  93. sum0=fffe0000,sum1=fffe0000
  94. DMA test OK
  95. DMA3 31000000h->31800000h,size=80000h(tc=20000h),dsz=2,burst=0
  96. DMA transfer done time=38 MS
  97. sum0=fffe0000,sum1=fffe0000
  98. DMA test OK
  99. DMA3 31000000h->31800000h,size=80000h(tc=20000h),dsz=0,burst=1
  100. DMA transfer done time=68 MS
  101. sum0=fffe0000,sum1=fffe0000
  102. DMA test OK
  103. DMA3 31000000h->31800000h,size=80000h(tc=10000h),dsz=1,burst=1
  104. DMA transfer done time=34 MS
  105. sum0=fffe0000,sum1=fffe0000
  106. DMA test OK
  107. DMA3 31000000h->31800000h,size=80000h(tc=8000h),dsz=2,burst=1
  108. DMA transfer done time=12 MS
  109. sum0=fffe0000,sum1=fffe0000
  110. DMA test OK
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