1、arch/arm/plat-s3c64xx/gpiolib.c文件中有如下：
arch_initcall(s3c64xx_gpiolib_init);這個應該實在系統初始化時調用。
static __init int s3c64xx_gpiolib_init(void)
{
s3c64xx_gpiolib_add(gpio_4bit, ARRAY_SIZE(gpio_4bit),
s3c64xx_gpiolib_add_4bit);
s3c64xx_gpiolib_add(gpio_4bit2, ARRAY_SIZE(gpio_4bit2),
s3c64xx_gpiolib_add_4bit2);
s3c64xx_gpiolib_add(gpio_2bit, ARRAY_SIZE(gpio_2bit), NULL);
return 0;
}
這三的藍色部分是什麼呢?看下面的源碼，應該知道其是個struct s3c_gpio_chip *chips結構體，在同一個文件中定義，現在原始的結構體：
/**
* struct s3c_gpio_chip - wrapper for specific implementation of gpio對具體GPIO的包裝
* @chip: The chip structure to be exported via gpiolib. 芯片的結構，配置通過gpiolib向外輸出
* @base: The base pointer to the gpio configuration registers.
* @config: special function and pull-resistor control information.
*
* This wrapper provides the necessary information for the Samsung
* specific gpios being registered with gpiolib.
*/
struct s3c_gpio_chip {
struct gpio_chip chip;
struct s3c_gpio_cfg*config;
void __iomem*base;
};
struct gpio_chip源碼如下：
/**
* struct gpio_chip - abstract a GPIO controller 對GPIO控制器的抽象
* @label: for diagnostics為判斷而設
* @dev: optional device providing the GPIOs
* @owner: helps prevent removal of modules exporting active GPIOs
* @request: optional hook for chip-specific activation, such as
*enabling module power and clock; may sleep
* @free: optional hook for chip-specific deactivation, such as
*disabling module power and clock; may sleep
* @direction_input: configures signal "offset" as input, or returns error
* @get: returns value for signal "offset"; for output signals this
*returns either the value actually sensed, or zero
* @direction_output: configures signal "offset" as output, or returns error
* @set: assigns output value for signal "offset"
* @to_irq: optional hook supporting non-static gpio_to_irq() mappings;
*implementation may not sleep
* @dbg_show: optional routine to show contents in debugfs; default code
*will be used when this is omitted, but custom code can show extra
*state (such as pullup/pulldown configuration).
* @base: identifies the first GPIO number handled by this chip; or, if
*negative during registration, requests dynamic ID allocation.
* @ngpio: the number of GPIOs handled by this controller; the last GPIO
*handled is (base + ngpio - 1).
* @can_sleep: flag must be set iff get()/set() methods sleep, as they
*must while accessing GPIO expander chips over I2C or SPI
*
* A gpio_chip can help platforms abstract various sources of GPIOs so
* they can all be accessed through a common programing interface.
幫助具體平台抽象各種GPIO來源，是能用統一的接口操作
* Example sources would be SOC controllers, FPGAs, multifunction
* chips, dedicated GPIO expanders, and so on.
*
* Each chip controls a number of signals, identified in method calls
* by "offset" values in the range 0..(@ngpio - 1). When those signals
* are referenced through calls like gpio_get_value(gpio), the offset
* is calculated by subtracting @base from the gpio number.
*/
struct gpio_chip {
const char*label;
struct device*dev;
struct module*owner;
int(*request)(struct gpio_chip *chip,
unsigned offset);
void(*free)(struct gpio_chip *chip,
unsigned offset);
int(*direction_input)(struct gpio_chip *chip,
unsigned offset);
int(*get)(struct gpio_chip *chip,
unsigned offset);
int(*direction_output)(struct gpio_chip *chip,
unsigned offset, int value);
void(*set)(struct gpio_chip *chip,
unsigned offset, int value);
int(*to_irq)(struct gpio_chip *chip,
unsigned offset);
void(*dbg_show)(struct seq_file *s,
struct gpio_chip *chip);
intbase;
u16ngpio;
unsignedcan_sleep:1;
unsignedexported:1;
};
再看具體的實例：
static struct s3c_gpio_chipgpio_4bit[] = {與上面第一個相對應
{
.base= S3C64XX_GPA_BASE,
.config= &gpio_4bit_cfg_eint0111,
.chip= {
.base= S3C64XX_GPA(0),
.ngpio= S3C64XX_GPIO_A_NR,
.label= "GPA",
},
}, {
.base= S3C64XX_GPB_BASE,
.config= &gpio_4bit_cfg_eint0111,
.chip= {
.base= S3C64XX_GPB(0),
.ngpio= S3C64XX_GPIO_B_NR,
.label= "GPB",
},
}, {
.base= S3C64XX_GPC_BASE,
.config= &gpio_4bit_cfg_eint0111,
.chip= {
.base= S3C64XX_GPC(0),
.ngpio= S3C64XX_GPIO_C_NR,
.label= "GPC",
},
}, {
.base= S3C64XX_GPD_BASE,
.config= &gpio_4bit_cfg_eint0111,
.chip= {
.base= S3C64XX_GPD(0),
.ngpio= S3C64XX_GPIO_D_NR,
.label= "GPD",
},
}, {
.base= S3C64XX_GPE_BASE,
.config= &gpio_4bit_cfg_noint,
.chip= {
.base= S3C64XX_GPE(0),
.ngpio= S3C64XX_GPIO_E_NR,
.label= "GPE",
},
}, {
.base= S3C64XX_GPG_BASE,
.config= &gpio_4bit_cfg_eint0111,
.chip= {
.base= S3C64XX_GPG(0),
.ngpio= S3C64XX_GPIO_G_NR,
.label= "GPG",
},
}, {
.base= S3C64XX_GPM_BASE,
.config= &gpio_4bit_cfg_eint0011,
.chip= {
.base= S3C64XX_GPM(0),
.ngpio= S3C64XX_GPIO_M_NR,
.label= "GPM",
},
},
};
