[signed][input]Verilog的有符號數輸入測試

git://github.com/adream307/signedTest.git

一直錯誤得以為Verilog中的數據是無符號的。

測試腳本，在QuartusII中成功編譯，且下載在硬件上運行。

1. //SIG.v
2. module SIG(
3. iCLK,
4. oSY,
5. oUY
6. );
8. input iCLK;
9. output [7:0] oSY;
10. output [7:0] oUY;
12. reg [7:0] x;
13. wire [3:0] x1 = x[3:0];
14. wire [3:0] x2 = x[7:4];
15. wire [7:0] sy;
16. wire [7:0] uy;
18. assign oSY = sy;
19. assign oUY = uy;
21. always@(negedge iCLK) begin
22. x<=x+8'd1;
23. end
25. SIGNED SIG_1(
26. .iX1(x1),
27. .iX2(x2),
28. .oY(sy)
29. );
31. UNSIGNED USIG_1(
32. .iX1(x1),
33. .iX2(x2),
34. .oY(uy)
35. );
37. endmodule

//SIG.v
module SIG(
	iCLK,
	oSY,
	oUY
);

input iCLK;
output [7:0] oSY;
output [7:0] oUY;

reg [7:0] x;
wire [3:0] x1 = x[3:0];
wire [3:0] x2 = x[7:4];
wire [7:0] sy;
wire [7:0] uy;

assign oSY = sy;
assign oUY = uy;

always@(negedge iCLK) begin
	x<=x+8'd1;
end

SIGNED SIG_1(
	.iX1(x1),
	.iX2(x2),
	.oY(sy)
);

UNSIGNED USIG_1(
	.iX1(x1),
	.iX2(x2),
	.oY(uy)
);

endmodule

1. //SIGNED.v
2. module SIGNED(
3. iX1,
4. iX2,
5. oY
6. );
8. input signed [3:0] iX1;
9. input signed [3:0] iX2;
10. output signed [7:0] oY;
12. assign oY = iX1*iX2;
14. endmodule

//SIGNED.v
module SIGNED(
	iX1,
	iX2,
	oY
);

input signed [3:0] iX1;
input signed [3:0] iX2;
output signed [7:0] oY;

assign oY = iX1*iX2;

endmodule

1. //UNSIGNED.v
2. module UNSIGNED(
3. iX1,
4. iX2,
5. oY
6. );
8. input [3:0] iX1;
9. input [3:0] iX2;
10. output [7:0] oY;
12. assign oY = iX1*iX2;
14. endmodule

//UNSIGNED.v
module UNSIGNED(
	iX1,
	iX2,
	oY
);

input [3:0] iX1;
input [3:0] iX2;
output [7:0] oY;

assign oY = iX1*iX2;

endmodule

上圖為SignalTapII的運行截圖，可以發現當x=0xFF時，此時x1=0xF，x2=0xF。

對於SIGNED，有符號運算,x1=-1,x2=-1，所以結果為1。

而對於UNSIGNED，無符號運算,x1=15,x2=15,所以結果為225，即0xE1。